In fabricating integrated circuits, forming many different films on Si wafers by physical vapor deposition (PVD) is one of the common steps. Currently there are many different configurations and methods in performing PVD process, for example ionized PVD and long-through-sputtering.
An angled sputtering is one of the PVD techniques where the target and wafer are placed not in parallel but with an angle. See JP 2002-194540. The advantage of this sputtering technique is it yields extremely uniform film. The disadvantage of this technique is that edge exclusion (hereinafter referred to “EE”) for a film deposited on a wafer surface trades-off with film wrapping around the wafer edge. This is explained in details with reference to FIGS. 5 to 9 of the present application.
A cross sectional diagram of an example of an angled sputtering system and a conventional wafer holder 50 adopted in the angled sputtering system are shown in FIGS. 5 to 8, respectively. The process chamber of this angled sputtering system has a vacuum port 66 and a wafer in/out port 67. The wafer holder 50 is comprised of wafer stage 51, insulating shield 52 surrounding wafer stage 51, metallic outer-shield 53, shaft 54 supporting the metallic outer-shield 53 and a masking outer-ring 55. The masking outer-ring 55 is attached to several metallic or insulating pins 56, usually 3 (three) metallic or insulating pins, in order to move the masking outer-ring 55 up and down. In FIG. 5, the insulating pins 56, 56 are moved up and down by lift-up pin controller 65.
While the wafer 57 is loaded on to the wafer stage 51, the masking outer-ring 55 is raised up. After the wafer 57 is placed on the wafer stage 51, the masking outer-ring 55 is lowered until the separation between the upper surface of wafer 57 and the backside surface of the masking outer-ring 55 is less than 1 mm. Usually, the masking outer-ring 55 is not lowered until the backside surface of it touches the wafer 57, since it causes a generation of particles on the surface of wafer 57 by the fraction. The masking outer-ring 55 covers a few millimeters, usually less than 5 mm, on the wafer edge 62 (FIG. 7). This covered region is denoted by X (denoted by numeral 63) in FIGS. 7 and 8.
The configuration of other conventional and commonly used wafer holder is given in FIG. 9 wherein there is no masking outer-ring.